Integrated semiconductor circuits including arrays or memories having, e.g., single transistor cells have achieved high cell densities.
In U.S Pat. No. 4,012,757, filed May 5, 1975, there is disclosed a one device per bit memory wherein the storage devices are grouped in pairs and share a common gate member and a common capacitive plate.
U.S. Pat. No. 4,125,854, filed Dec. 2, 1976, teaches a static random access memory array wherein a common drain supply node is centrally disposed within a group of four mutually contiguous cells.
Commonly assigned U.S. Pat. No. 4,287,571, filed on Sept. 11, 1979, by S. N. Chakravarti and J. A. Hiltebeitel, discloses a dense read only memory (ROM) having one contact shared by four cells.
U.S. Pat. No. 4,376,983, filed Mar. 21, 1980, describes an array of one device dynamic memory cells which uses three levels of polysilicon with zigzag lines to achieve high density.